/*
 * Copyright (c) 2011 Intel Corporation. All Rights Reserved.
 * Copyright (c) Imagination Technologies Limited, UK
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */


/******************************************************************************

 @File         msvdx_vdmc_reg_io2.h

 @Title        MSVDX Offsets

 @Platform     </b>\n

 @Description  </b>\n This file contains the MSVDX_VDMC_REG_IO2_H Defintions.

******************************************************************************/
#if !defined (__MSVDX_VDMC_REG_IO2_H__)
#define __MSVDX_VDMC_REG_IO2_H__

#ifdef __cplusplus
extern "C" {
#endif


#define MSVDX_VDMC_CR_VDMC_REFERENCE_CACHE_SIGNATURE_OFFSET             (0x0000)

// MSVDX_VDMC     CR_VDMC_REFERENCE_CACHE_SIGNATURE     CR_VDMC_REFCACHE_SIG
#define MSVDX_VDMC_CR_VDMC_REFERENCE_CACHE_SIGNATURE_CR_VDMC_REFCACHE_SIG_MASK          (0xFFFFFFFF)
#define MSVDX_VDMC_CR_VDMC_REFERENCE_CACHE_SIGNATURE_CR_VDMC_REFCACHE_SIG_LSBMASK               (0xFFFFFFFF)
#define MSVDX_VDMC_CR_VDMC_REFERENCE_CACHE_SIGNATURE_CR_VDMC_REFCACHE_SIG_SHIFT         (0)

#define MSVDX_VDMC_CR_VDMC_REFERENCE_CACHE_EFFICIENCY_OFFSET            (0x0004)

// MSVDX_VDMC     CR_VDMC_REFERENCE_CACHE_EFFICIENCY     CR_VDMC_REFCACHE_EFFICIENCY
#define MSVDX_VDMC_CR_VDMC_REFERENCE_CACHE_EFFICIENCY_CR_VDMC_REFCACHE_EFFICIENCY_MASK          (0xFFFFFFFF)
#define MSVDX_VDMC_CR_VDMC_REFERENCE_CACHE_EFFICIENCY_CR_VDMC_REFCACHE_EFFICIENCY_LSBMASK               (0xFFFFFFFF)
#define MSVDX_VDMC_CR_VDMC_REFERENCE_CACHE_EFFICIENCY_CR_VDMC_REFCACHE_EFFICIENCY_SHIFT         (0)

#define MSVDX_VDMC_CR_VDMC_2D_FILTER_PIPELINE_SIGNATURE_OFFSET          (0x0008)

// MSVDX_VDMC     CR_VDMC_2D_FILTER_PIPELINE_SIGNATURE     CR_VDMC_FILT_SIG
#define MSVDX_VDMC_CR_VDMC_2D_FILTER_PIPELINE_SIGNATURE_CR_VDMC_FILT_SIG_MASK           (0xFFFFFFFF)
#define MSVDX_VDMC_CR_VDMC_2D_FILTER_PIPELINE_SIGNATURE_CR_VDMC_FILT_SIG_LSBMASK                (0xFFFFFFFF)
#define MSVDX_VDMC_CR_VDMC_2D_FILTER_PIPELINE_SIGNATURE_CR_VDMC_FILT_SIG_SHIFT          (0)

#define MSVDX_VDMC_CR_VDMC_PIXEL_RECONSTRUCTION_SIGNATURE_OFFSET                (0x000C)

// MSVDX_VDMC     CR_VDMC_PIXEL_RECONSTRUCTION_SIGNATURE     CR_VDMC_RECON_SIG
#define MSVDX_VDMC_CR_VDMC_PIXEL_RECONSTRUCTION_SIGNATURE_CR_VDMC_RECON_SIG_MASK                (0xFFFFFFFF)
#define MSVDX_VDMC_CR_VDMC_PIXEL_RECONSTRUCTION_SIGNATURE_CR_VDMC_RECON_SIG_LSBMASK             (0xFFFFFFFF)
#define MSVDX_VDMC_CR_VDMC_PIXEL_RECONSTRUCTION_SIGNATURE_CR_VDMC_RECON_SIG_SHIFT               (0)

#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_OFFSET          (0x0010)

// MSVDX_VDMC     CR_VDMC_ERROR_STATUS     CR_VDMC_SLICE_REALIGNMENT
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_SLICE_REALIGNMENT_MASK          (0x00010000)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_SLICE_REALIGNMENT_LSBMASK               (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_SLICE_REALIGNMENT_SHIFT         (16)

// MSVDX_VDMC     CR_VDMC_ERROR_STATUS     CR_VDMC_SLICE_LATE_ERROR
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_SLICE_LATE_ERROR_MASK           (0x00008000)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_SLICE_LATE_ERROR_LSBMASK                (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_SLICE_LATE_ERROR_SHIFT          (15)

// MSVDX_VDMC     CR_VDMC_ERROR_STATUS     CR_VDMC_SLICE_EARLY_ERROR
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_SLICE_EARLY_ERROR_MASK          (0x00004000)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_SLICE_EARLY_ERROR_LSBMASK               (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_SLICE_EARLY_ERROR_SHIFT         (14)

// MSVDX_VDMC     CR_VDMC_ERROR_STATUS     CR_VDMC_MB_ALIGNMENT_ERROR
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_MB_ALIGNMENT_ERROR_MASK         (0x00002000)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_MB_ALIGNMENT_ERROR_LSBMASK              (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_MB_ALIGNMENT_ERROR_SHIFT                (13)

// MSVDX_VDMC     CR_VDMC_ERROR_STATUS     CR_VDMC_FILT_SYNC_ERROR
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_FILT_SYNC_ERROR_MASK            (0x00001000)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_FILT_SYNC_ERROR_LSBMASK         (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_FILT_SYNC_ERROR_SHIFT           (12)

// MSVDX_VDMC     CR_VDMC_ERROR_STATUS     CR_VDMC_READ_OVERFLOW
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_READ_OVERFLOW_MASK              (0x00000800)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_READ_OVERFLOW_LSBMASK           (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_READ_OVERFLOW_SHIFT             (11)

// MSVDX_VDMC     CR_VDMC_ERROR_STATUS     CR_VDMC_INTER_INTRA_ERROR
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_INTER_INTRA_ERROR_MASK          (0x00000400)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_INTER_INTRA_ERROR_LSBMASK               (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_INTER_INTRA_ERROR_SHIFT         (10)

// MSVDX_VDMC     CR_VDMC_ERROR_STATUS     CR_VDMC_MBNO_SMALL_ERROR
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_MBNO_SMALL_ERROR_MASK           (0x00000200)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_MBNO_SMALL_ERROR_LSBMASK                (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_MBNO_SMALL_ERROR_SHIFT          (9)

// MSVDX_VDMC     CR_VDMC_ERROR_STATUS     CR_VDMC_MBNO_LARGE_ERROR
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_MBNO_LARGE_ERROR_MASK           (0x00000100)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_MBNO_LARGE_ERROR_LSBMASK                (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_MBNO_LARGE_ERROR_SHIFT          (8)

// MSVDX_VDMC     CR_VDMC_ERROR_STATUS     CR_VDMC_INTRAMV_ERROR
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_INTRAMV_ERROR_MASK              (0x00000080)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_INTRAMV_ERROR_LSBMASK           (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_INTRAMV_ERROR_SHIFT             (7)

// MSVDX_VDMC     CR_VDMC_ERROR_STATUS     CR_VDMC_MVACC_ERROR
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_MVACC_ERROR_MASK                (0x00000040)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_MVACC_ERROR_LSBMASK             (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_MVACC_ERROR_SHIFT               (6)

// MSVDX_VDMC     CR_VDMC_ERROR_STATUS     CR_VDMC_MVSIZE_ERROR
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_MVSIZE_ERROR_MASK               (0x00000020)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_MVSIZE_ERROR_LSBMASK            (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_MVSIZE_ERROR_SHIFT              (5)

// MSVDX_VDMC     CR_VDMC_ERROR_STATUS     CR_VDMC_NOOFMV_FEW
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_NOOFMV_FEW_MASK         (0x00000010)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_NOOFMV_FEW_LSBMASK              (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_NOOFMV_FEW_SHIFT                (4)

// MSVDX_VDMC     CR_VDMC_ERROR_STATUS     CR_VDMC_NOOFMV_MANY
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_NOOFMV_MANY_MASK                (0x00000008)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_NOOFMV_MANY_LSBMASK             (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_NOOFMV_MANY_SHIFT               (3)

// MSVDX_VDMC     CR_VDMC_ERROR_STATUS     CR_VDMC_NOOFBLK_FEW
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_NOOFBLK_FEW_MASK                (0x00000004)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_NOOFBLK_FEW_LSBMASK             (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_NOOFBLK_FEW_SHIFT               (2)

// MSVDX_VDMC     CR_VDMC_ERROR_STATUS     CR_VDMC_NOOFBLK_MANY
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_NOOFBLK_MANY_MASK               (0x00000002)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_NOOFBLK_MANY_LSBMASK            (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_NOOFBLK_MANY_SHIFT              (1)

// MSVDX_VDMC     CR_VDMC_ERROR_STATUS     CR_VDMC_MBNO_PICTSIZE_MISMATCH
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_MBNO_PICTSIZE_MISMATCH_MASK             (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_MBNO_PICTSIZE_MISMATCH_LSBMASK          (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ERROR_STATUS_CR_VDMC_MBNO_PICTSIZE_MISMATCH_SHIFT            (0)

#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_OFFSET                (0x0014)

// MSVDX_VDMC     CR_VDMC_ENAB_INTERRUPT     CR_VDMC_ENAB_SLICE_REALIGNMENT
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_SLICE_REALIGNMENT_MASK           (0x00010000)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_SLICE_REALIGNMENT_LSBMASK                (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_SLICE_REALIGNMENT_SHIFT          (16)

// MSVDX_VDMC     CR_VDMC_ENAB_INTERRUPT     CR_VDMC_ENAB_SLICE_LATE_ERROR
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_SLICE_LATE_ERROR_MASK            (0x00008000)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_SLICE_LATE_ERROR_LSBMASK         (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_SLICE_LATE_ERROR_SHIFT           (15)

// MSVDX_VDMC     CR_VDMC_ENAB_INTERRUPT     CR_VDMC_ENAB_SLICE_EARLY_ERROR
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_SLICE_EARLY_ERROR_MASK           (0x00004000)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_SLICE_EARLY_ERROR_LSBMASK                (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_SLICE_EARLY_ERROR_SHIFT          (14)

// MSVDX_VDMC     CR_VDMC_ENAB_INTERRUPT     CR_VDMC_ENAB_MB_ALIGN_ERROR
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_MB_ALIGN_ERROR_MASK              (0x00002000)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_MB_ALIGN_ERROR_LSBMASK           (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_MB_ALIGN_ERROR_SHIFT             (13)

// MSVDX_VDMC     CR_VDMC_ENAB_INTERRUPT     CR_VDMC_ENAB_FILT_SYNC_ERROR
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_FILT_SYNC_ERROR_MASK             (0x00001000)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_FILT_SYNC_ERROR_LSBMASK          (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_FILT_SYNC_ERROR_SHIFT            (12)

// MSVDX_VDMC     CR_VDMC_ENAB_INTERRUPT     CR_VDMC_ENAB_READ_OVERFLOW
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_READ_OVERFLOW_MASK               (0x00000800)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_READ_OVERFLOW_LSBMASK            (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_READ_OVERFLOW_SHIFT              (11)

// MSVDX_VDMC     CR_VDMC_ENAB_INTERRUPT     CR_VDMC_ENAB_INTER_INTRA_ERROR
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_INTER_INTRA_ERROR_MASK           (0x00000400)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_INTER_INTRA_ERROR_LSBMASK                (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_INTER_INTRA_ERROR_SHIFT          (10)

// MSVDX_VDMC     CR_VDMC_ENAB_INTERRUPT     CR_VDMC_ENAB_MBNO_SMALL_ERROR
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_MBNO_SMALL_ERROR_MASK            (0x00000200)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_MBNO_SMALL_ERROR_LSBMASK         (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_MBNO_SMALL_ERROR_SHIFT           (9)

// MSVDX_VDMC     CR_VDMC_ENAB_INTERRUPT     CR_VDMC_ENAB_MBNO_LARGE_ERROR
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_MBNO_LARGE_ERROR_MASK            (0x00000100)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_MBNO_LARGE_ERROR_LSBMASK         (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_MBNO_LARGE_ERROR_SHIFT           (8)

// MSVDX_VDMC     CR_VDMC_ENAB_INTERRUPT     CR_VDMC_ENAB_INTRAMV_ERROR
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_INTRAMV_ERROR_MASK               (0x00000080)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_INTRAMV_ERROR_LSBMASK            (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_INTRAMV_ERROR_SHIFT              (7)

// MSVDX_VDMC     CR_VDMC_ENAB_INTERRUPT     CR_VDMC_ENAB_MVACC_ERROR
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_MVACC_ERROR_MASK         (0x00000040)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_MVACC_ERROR_LSBMASK              (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_MVACC_ERROR_SHIFT                (6)

// MSVDX_VDMC     CR_VDMC_ENAB_INTERRUPT     CR_VDMC_ENAB_MVSIZE_ERROR
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_MVSIZE_ERROR_MASK                (0x00000020)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_MVSIZE_ERROR_LSBMASK             (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_MVSIZE_ERROR_SHIFT               (5)

// MSVDX_VDMC     CR_VDMC_ENAB_INTERRUPT     CR_VDMC_ENAB_NOOFMV_FEW
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_NOOFMV_FEW_MASK          (0x00000010)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_NOOFMV_FEW_LSBMASK               (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_NOOFMV_FEW_SHIFT         (4)

// MSVDX_VDMC     CR_VDMC_ENAB_INTERRUPT     CR_VDMC_ENAB_NOOFMV_MANY
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_NOOFMV_MANY_MASK         (0x00000008)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_NOOFMV_MANY_LSBMASK              (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_NOOFMV_MANY_SHIFT                (3)

// MSVDX_VDMC     CR_VDMC_ENAB_INTERRUPT     CR_VDMC_EANB_NOOFBLK_FEW
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_EANB_NOOFBLK_FEW_MASK         (0x00000004)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_EANB_NOOFBLK_FEW_LSBMASK              (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_EANB_NOOFBLK_FEW_SHIFT                (2)

// MSVDX_VDMC     CR_VDMC_ENAB_INTERRUPT     CR_VDMC_ENAB_NOOFBLK_MANY
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_NOOFBLK_MANY_MASK                (0x00000002)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_NOOFBLK_MANY_LSBMASK             (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_NOOFBLK_MANY_SHIFT               (1)

// MSVDX_VDMC     CR_VDMC_ENAB_INTERRUPT     CR_VDMC_ENAB_MBNO_PICTSIZE_MISMATCH
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_MBNO_PICTSIZE_MISMATCH_MASK              (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_MBNO_PICTSIZE_MISMATCH_LSBMASK           (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ENAB_INTERRUPT_CR_VDMC_ENAB_MBNO_PICTSIZE_MISMATCH_SHIFT             (0)

#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_OFFSET            (0x0018)

// MSVDX_VDMC     CR_VDMC_CLR_STATUS     CR_VDMC_CLR_SLICE_REALIGNMENT
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_SLICE_REALIGNMENT_MASK                (0x00010000)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_SLICE_REALIGNMENT_LSBMASK             (0x00000001)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_SLICE_REALIGNMENT_SHIFT               (16)

// MSVDX_VDMC     CR_VDMC_CLR_STATUS     CR_VDMC_CLR_SLICE_LATE_ERROR
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_SLICE_LATE_ERROR_MASK         (0x00008000)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_SLICE_LATE_ERROR_LSBMASK              (0x00000001)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_SLICE_LATE_ERROR_SHIFT                (15)

// MSVDX_VDMC     CR_VDMC_CLR_STATUS     CR_VDMC_CLR_SLICE_EARLY_ERROR
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_SLICE_EARLY_ERROR_MASK                (0x00004000)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_SLICE_EARLY_ERROR_LSBMASK             (0x00000001)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_SLICE_EARLY_ERROR_SHIFT               (14)

// MSVDX_VDMC     CR_VDMC_CLR_STATUS     CR_VDMC_CLR_MB_ALIGN_ERROR
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_MB_ALIGN_ERROR_MASK           (0x00002000)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_MB_ALIGN_ERROR_LSBMASK                (0x00000001)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_MB_ALIGN_ERROR_SHIFT          (13)

// MSVDX_VDMC     CR_VDMC_CLR_STATUS     CR_VDMC_CLR_FILT_SYNC_ERROR
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_FILT_SYNC_ERROR_MASK          (0x00001000)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_FILT_SYNC_ERROR_LSBMASK               (0x00000001)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_FILT_SYNC_ERROR_SHIFT         (12)

// MSVDX_VDMC     CR_VDMC_CLR_STATUS     CR_VDMC_CLR_READ_OVERFLOW
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_READ_OVERFLOW_MASK            (0x00000800)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_READ_OVERFLOW_LSBMASK         (0x00000001)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_READ_OVERFLOW_SHIFT           (11)

// MSVDX_VDMC     CR_VDMC_CLR_STATUS     CR_VDMC_CLR_INTER_INTRA_ERROR
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_INTER_INTRA_ERROR_MASK                (0x00000400)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_INTER_INTRA_ERROR_LSBMASK             (0x00000001)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_INTER_INTRA_ERROR_SHIFT               (10)

// MSVDX_VDMC     CR_VDMC_CLR_STATUS     CR_VDMC_CLR_MBNO_SMALL_ERROR
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_MBNO_SMALL_ERROR_MASK         (0x00000200)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_MBNO_SMALL_ERROR_LSBMASK              (0x00000001)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_MBNO_SMALL_ERROR_SHIFT                (9)

// MSVDX_VDMC     CR_VDMC_CLR_STATUS     CR_VDMC_CLR_MBNO_LARGE_ERROR
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_MBNO_LARGE_ERROR_MASK         (0x00000100)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_MBNO_LARGE_ERROR_LSBMASK              (0x00000001)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_MBNO_LARGE_ERROR_SHIFT                (8)

// MSVDX_VDMC     CR_VDMC_CLR_STATUS     CR_VDMC_CLR_INTRAMV_ERROR
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_INTRAMV_ERROR_MASK            (0x00000080)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_INTRAMV_ERROR_LSBMASK         (0x00000001)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_INTRAMV_ERROR_SHIFT           (7)

// MSVDX_VDMC     CR_VDMC_CLR_STATUS     CR_VDMC_CLR_MVACC_ERROR
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_MVACC_ERROR_MASK              (0x00000040)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_MVACC_ERROR_LSBMASK           (0x00000001)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_MVACC_ERROR_SHIFT             (6)

// MSVDX_VDMC     CR_VDMC_CLR_STATUS     CR_VDMC_CLR_MVSIZE_ERROR
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_MVSIZE_ERROR_MASK             (0x00000020)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_MVSIZE_ERROR_LSBMASK          (0x00000001)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_MVSIZE_ERROR_SHIFT            (5)

// MSVDX_VDMC     CR_VDMC_CLR_STATUS     CR_VDMC_CLR_NOOFMV_FEW
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_NOOFMV_FEW_MASK               (0x00000010)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_NOOFMV_FEW_LSBMASK            (0x00000001)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_NOOFMV_FEW_SHIFT              (4)

// MSVDX_VDMC     CR_VDMC_CLR_STATUS     CR_VDMC_CLR_NOOFMV_MANY
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_NOOFMV_MANY_MASK              (0x00000008)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_NOOFMV_MANY_LSBMASK           (0x00000001)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_NOOFMV_MANY_SHIFT             (3)

// MSVDX_VDMC     CR_VDMC_CLR_STATUS     CR_VDMC_CLR_NOOFBLK_FEW
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_NOOFBLK_FEW_MASK              (0x00000004)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_NOOFBLK_FEW_LSBMASK           (0x00000001)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_NOOFBLK_FEW_SHIFT             (2)

// MSVDX_VDMC     CR_VDMC_CLR_STATUS     CR_VDMC_CLR_NOOFBLK_MANY
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_NOOFBLK_MANY_MASK             (0x00000002)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_NOOFBLK_MANY_LSBMASK          (0x00000001)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_NOOFBLK_MANY_SHIFT            (1)

// MSVDX_VDMC     CR_VDMC_CLR_STATUS     CR_VDMC_CLR_MBNO_PICTSIZE_MISMATCH
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_MBNO_PICTSIZE_MISMATCH_MASK           (0x00000001)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_MBNO_PICTSIZE_MISMATCH_LSBMASK                (0x00000001)
#define MSVDX_VDMC_CR_VDMC_CLR_STATUS_CR_VDMC_CLR_MBNO_PICTSIZE_MISMATCH_SHIFT          (0)

#define MSVDX_VDMC_CR_VDMC_2D_FILTER_PIPELINE_DIRECT_INSERT_DATA_OFFSET         (0x0020)

// MSVDX_VDMC     CR_VDMC_2D_FILTER_PIPELINE_DIRECT_INSERT_DATA     CR_VDMC_FILT_DIRECT_DATA
#define MSVDX_VDMC_CR_VDMC_2D_FILTER_PIPELINE_DIRECT_INSERT_DATA_CR_VDMC_FILT_DIRECT_DATA_MASK          (0xFFFFFFFF)
#define MSVDX_VDMC_CR_VDMC_2D_FILTER_PIPELINE_DIRECT_INSERT_DATA_CR_VDMC_FILT_DIRECT_DATA_LSBMASK               (0xFFFFFFFF)
#define MSVDX_VDMC_CR_VDMC_2D_FILTER_PIPELINE_DIRECT_INSERT_DATA_CR_VDMC_FILT_DIRECT_DATA_SHIFT         (0)

#define MSVDX_VDMC_CR_VDMC_2D_FILTER_PIPELINE_DIRECT_INSERT_CONTROL_OFFSET              (0x0024)

// MSVDX_VDMC     CR_VDMC_2D_FILTER_PIPELINE_DIRECT_INSERT_CONTROL     CR_VDMC_FILT_DIRECT_CONTROL
#define MSVDX_VDMC_CR_VDMC_2D_FILTER_PIPELINE_DIRECT_INSERT_CONTROL_CR_VDMC_FILT_DIRECT_CONTROL_MASK            (0xFFFFFFFF)
#define MSVDX_VDMC_CR_VDMC_2D_FILTER_PIPELINE_DIRECT_INSERT_CONTROL_CR_VDMC_FILT_DIRECT_CONTROL_LSBMASK         (0xFFFFFFFF)
#define MSVDX_VDMC_CR_VDMC_2D_FILTER_PIPELINE_DIRECT_INSERT_CONTROL_CR_VDMC_FILT_DIRECT_CONTROL_SHIFT           (0)

#define MSVDX_VDMC_CR_VDMC_PIXEL_RECONSTRUCTION_DIRECT_INSERT_DATA_OFFSET               (0x0028)

// MSVDX_VDMC     CR_VDMC_PIXEL_RECONSTRUCTION_DIRECT_INSERT_DATA     CR_VDMC_RECON_DIRECT_DATA
#define MSVDX_VDMC_CR_VDMC_PIXEL_RECONSTRUCTION_DIRECT_INSERT_DATA_CR_VDMC_RECON_DIRECT_DATA_MASK               (0xFFFFFFFF)
#define MSVDX_VDMC_CR_VDMC_PIXEL_RECONSTRUCTION_DIRECT_INSERT_DATA_CR_VDMC_RECON_DIRECT_DATA_LSBMASK            (0xFFFFFFFF)
#define MSVDX_VDMC_CR_VDMC_PIXEL_RECONSTRUCTION_DIRECT_INSERT_DATA_CR_VDMC_RECON_DIRECT_DATA_SHIFT              (0)

#define MSVDX_VDMC_CR_VDMC_PIXEL_RECONSTRUCTION_DIRECT_INSERT_CONTROL_OFFSET            (0x002C)

// MSVDX_VDMC     CR_VDMC_PIXEL_RECONSTRUCTION_DIRECT_INSERT_CONTROL     CR_VDMC_RECON_DIRECT_CONTROL
#define MSVDX_VDMC_CR_VDMC_PIXEL_RECONSTRUCTION_DIRECT_INSERT_CONTROL_CR_VDMC_RECON_DIRECT_CONTROL_MASK         (0x00007FFF)
#define MSVDX_VDMC_CR_VDMC_PIXEL_RECONSTRUCTION_DIRECT_INSERT_CONTROL_CR_VDMC_RECON_DIRECT_CONTROL_LSBMASK              (0x00007FFF)
#define MSVDX_VDMC_CR_VDMC_PIXEL_RECONSTRUCTION_DIRECT_INSERT_CONTROL_CR_VDMC_RECON_DIRECT_CONTROL_SHIFT                (0)

#define MSVDX_VDMC_CR_VDMC_RESIDUAL_DIRECT_INSERT_DATA_OFFSET           (0x0030)

// MSVDX_VDMC     CR_VDMC_RESIDUAL_DIRECT_INSERT_DATA     CR_VDMC_RESIDUAL_DIRECT_DATA
#define MSVDX_VDMC_CR_VDMC_RESIDUAL_DIRECT_INSERT_DATA_CR_VDMC_RESIDUAL_DIRECT_DATA_MASK                (0xFFFFFFFF)
#define MSVDX_VDMC_CR_VDMC_RESIDUAL_DIRECT_INSERT_DATA_CR_VDMC_RESIDUAL_DIRECT_DATA_LSBMASK             (0xFFFFFFFF)
#define MSVDX_VDMC_CR_VDMC_RESIDUAL_DIRECT_INSERT_DATA_CR_VDMC_RESIDUAL_DIRECT_DATA_SHIFT               (0)

#define MSVDX_VDMC_CR_VDMC_RESIDUAL_DIRECT_INSERT_CONTROL_OFFSET                (0x0034)

// MSVDX_VDMC     CR_VDMC_RESIDUAL_DIRECT_INSERT_CONTROL     CR_VDMC_RESIDUAL_DIRECT_CONTROL
#define MSVDX_VDMC_CR_VDMC_RESIDUAL_DIRECT_INSERT_CONTROL_CR_VDMC_RESIDUAL_DIRECT_CONTROL_MASK          (0x00000001)
#define MSVDX_VDMC_CR_VDMC_RESIDUAL_DIRECT_INSERT_CONTROL_CR_VDMC_RESIDUAL_DIRECT_CONTROL_LSBMASK               (0x00000001)
#define MSVDX_VDMC_CR_VDMC_RESIDUAL_DIRECT_INSERT_CONTROL_CR_VDMC_RESIDUAL_DIRECT_CONTROL_SHIFT         (0)

// MSVDX_VDMC     CR_VDMC_RESIDUAL_DIRECT_INSERT_CONTROL     CR_VDMC_RESIDUAL_DISABLE_MB_CHECK
#define MSVDX_VDMC_CR_VDMC_RESIDUAL_DIRECT_INSERT_CONTROL_CR_VDMC_RESIDUAL_DISABLE_MB_CHECK_MASK                (0x00000002)
#define MSVDX_VDMC_CR_VDMC_RESIDUAL_DIRECT_INSERT_CONTROL_CR_VDMC_RESIDUAL_DISABLE_MB_CHECK_LSBMASK             (0x00000001)
#define MSVDX_VDMC_CR_VDMC_RESIDUAL_DIRECT_INSERT_CONTROL_CR_VDMC_RESIDUAL_DISABLE_MB_CHECK_SHIFT               (1)

// MSVDX_VDMC     CR_VDMC_RESIDUAL_DIRECT_INSERT_CONTROL     CR_VDMC_ADD_128_INTRA_IN_INTER
#define MSVDX_VDMC_CR_VDMC_RESIDUAL_DIRECT_INSERT_CONTROL_CR_VDMC_ADD_128_INTRA_IN_INTER_MASK           (0x00000004)
#define MSVDX_VDMC_CR_VDMC_RESIDUAL_DIRECT_INSERT_CONTROL_CR_VDMC_ADD_128_INTRA_IN_INTER_LSBMASK                (0x00000001)
#define MSVDX_VDMC_CR_VDMC_RESIDUAL_DIRECT_INSERT_CONTROL_CR_VDMC_ADD_128_INTRA_IN_INTER_SHIFT          (2)

// MSVDX_VDMC     CR_VDMC_RESIDUAL_DIRECT_INSERT_CONTROL     CR_VDMC_HD_SUPPORTED
#define MSVDX_VDMC_CR_VDMC_RESIDUAL_DIRECT_INSERT_CONTROL_CR_VDMC_HD_SUPPORTED_MASK             (0x80000000)
#define MSVDX_VDMC_CR_VDMC_RESIDUAL_DIRECT_INSERT_CONTROL_CR_VDMC_HD_SUPPORTED_LSBMASK          (0x00000001)
#define MSVDX_VDMC_CR_VDMC_RESIDUAL_DIRECT_INSERT_CONTROL_CR_VDMC_HD_SUPPORTED_SHIFT            (31)

#define MSVDX_VDMC_CR_VDMC_LUMA_ERROR_BASE_ADDR_OFFSET          (0x0040)

// MSVDX_VDMC     CR_VDMC_LUMA_ERROR_BASE_ADDR     CR_VDMC_LUMA_ERROR_BASE
#define MSVDX_VDMC_CR_VDMC_LUMA_ERROR_BASE_ADDR_CR_VDMC_LUMA_ERROR_BASE_MASK            (0xFFFFF000)
#define MSVDX_VDMC_CR_VDMC_LUMA_ERROR_BASE_ADDR_CR_VDMC_LUMA_ERROR_BASE_LSBMASK         (0x000FFFFF)
#define MSVDX_VDMC_CR_VDMC_LUMA_ERROR_BASE_ADDR_CR_VDMC_LUMA_ERROR_BASE_SHIFT           (12)

#define MSVDX_VDMC_CR_VDMC_CHROMA_ERROR_BASE_ADDR_OFFSET                (0x0044)

// MSVDX_VDMC     CR_VDMC_CHROMA_ERROR_BASE_ADDR     CR_VDMC_CHROMA_ERROR_BASE
#define MSVDX_VDMC_CR_VDMC_CHROMA_ERROR_BASE_ADDR_CR_VDMC_CHROMA_ERROR_BASE_MASK                (0xFFFFF000)
#define MSVDX_VDMC_CR_VDMC_CHROMA_ERROR_BASE_ADDR_CR_VDMC_CHROMA_ERROR_BASE_LSBMASK             (0x000FFFFF)
#define MSVDX_VDMC_CR_VDMC_CHROMA_ERROR_BASE_ADDR_CR_VDMC_CHROMA_ERROR_BASE_SHIFT               (12)

#define MSVDX_VDMC_CR_VDMC_MACROBLOCK_NUMBER_OFFSET             (0x0048)

// MSVDX_VDMC     CR_VDMC_MACROBLOCK_NUMBER     CR_VDMC_MACROBLOCK_Y_OFFSET
#define MSVDX_VDMC_CR_VDMC_MACROBLOCK_NUMBER_CR_VDMC_MACROBLOCK_Y_OFFSET_MASK           (0x0000FF00)
#define MSVDX_VDMC_CR_VDMC_MACROBLOCK_NUMBER_CR_VDMC_MACROBLOCK_Y_OFFSET_LSBMASK                (0x000000FF)
#define MSVDX_VDMC_CR_VDMC_MACROBLOCK_NUMBER_CR_VDMC_MACROBLOCK_Y_OFFSET_SHIFT          (8)

// MSVDX_VDMC     CR_VDMC_MACROBLOCK_NUMBER     CR_VDMC_MACROBLOCK_X_OFFSET
#define MSVDX_VDMC_CR_VDMC_MACROBLOCK_NUMBER_CR_VDMC_MACROBLOCK_X_OFFSET_MASK           (0x000000FF)
#define MSVDX_VDMC_CR_VDMC_MACROBLOCK_NUMBER_CR_VDMC_MACROBLOCK_X_OFFSET_LSBMASK                (0x000000FF)
#define MSVDX_VDMC_CR_VDMC_MACROBLOCK_NUMBER_CR_VDMC_MACROBLOCK_X_OFFSET_SHIFT          (0)

#define MSVDX_VDMC_CR_VDMC_ERROR_FLUSH_CTRL_OFFSET              (0x004C)

// MSVDX_VDMC     CR_VDMC_ERROR_FLUSH_CTRL     CR_VDMC_ERROR_DETECTED_FLAG
#define MSVDX_VDMC_CR_VDMC_ERROR_FLUSH_CTRL_CR_VDMC_ERROR_DETECTED_FLAG_MASK            (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ERROR_FLUSH_CTRL_CR_VDMC_ERROR_DETECTED_FLAG_LSBMASK         (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ERROR_FLUSH_CTRL_CR_VDMC_ERROR_DETECTED_FLAG_SHIFT           (0)

// MSVDX_VDMC     CR_VDMC_ERROR_FLUSH_CTRL     CR_VDMC_SLICE_FLUSH_FLAG
#define MSVDX_VDMC_CR_VDMC_ERROR_FLUSH_CTRL_CR_VDMC_SLICE_FLUSH_FLAG_MASK               (0x00000002)
#define MSVDX_VDMC_CR_VDMC_ERROR_FLUSH_CTRL_CR_VDMC_SLICE_FLUSH_FLAG_LSBMASK            (0x00000001)
#define MSVDX_VDMC_CR_VDMC_ERROR_FLUSH_CTRL_CR_VDMC_SLICE_FLUSH_FLAG_SHIFT              (1)

#define MSVDX_VDMC_CR_VDMC_MCU_SIGNATURE_OFFSET         (0x0050)

// MSVDX_VDMC     CR_VDMC_MCU_SIGNATURE     CR_VDMC_MCU_SIG
#define MSVDX_VDMC_CR_VDMC_MCU_SIGNATURE_CR_VDMC_MCU_SIG_MASK           (0xFFFFFFFF)
#define MSVDX_VDMC_CR_VDMC_MCU_SIGNATURE_CR_VDMC_MCU_SIG_LSBMASK                (0xFFFFFFFF)
#define MSVDX_VDMC_CR_VDMC_MCU_SIGNATURE_CR_VDMC_MCU_SIG_SHIFT          (0)

#define MSVDX_VDMC_CR_VDMC_RES_BUFFER_WRITES_OFFSET             (0x0054)

// MSVDX_VDMC     CR_VDMC_RES_BUFFER_WRITES     CR_VDMC_RES_WRITES
#define MSVDX_VDMC_CR_VDMC_RES_BUFFER_WRITES_CR_VDMC_RES_WRITES_MASK            (0xFFFFFFFF)
#define MSVDX_VDMC_CR_VDMC_RES_BUFFER_WRITES_CR_VDMC_RES_WRITES_LSBMASK         (0xFFFFFFFF)
#define MSVDX_VDMC_CR_VDMC_RES_BUFFER_WRITES_CR_VDMC_RES_WRITES_SHIFT           (0)



#ifdef __cplusplus
}
#endif

#endif /* __MSVDX_VDMC_REG_IO2_H__ */
